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989 IP
501
0.118
UMC 28nm HPC process 2PRF with LVT and Bank 2
UMC 28nm HPC process 2PRF with LVT and Bank 2...
502
0.118
UMC 28nm HPC process 2PRF, HVT & Bank2
UMC 28nm HPC process 2PRF, HVT & Bank2...
503
0.118
UMC 28nm HPC process Dual Port SRAM compiler
UMC 28nm HPC process Dual Port SRAM compiler...
504
0.118
UMC 28nm HPC process Dual Port SRAM compiler
UMC 28nm HPC process Dual Port SRAM compiler...
505
0.118
UMC 28nm HPC process Dual Port SRAM compiler
UMC 28nm HPC process Dual Port SRAM compiler...
506
0.118
UMC 28nm HPC process Dual Port SRAM with LVT
UMC 28nm HPC process Dual Port SRAM with LVT...
507
0.118
UMC 28nm HPC process Dual Port SRAM with Power gating
UMC 28nm HPC process Dual Port SRAM with Power gating...
508
0.118
UMC 28nm HPC Process dual port SRAM with power gating
UMC 28nm HPC Process dual port SRAM with power gating...
509
0.118
UMC 28nm HPC process Dual Port SRAM with row reapir
UMC 28nm HPC process Dual Port SRAM with row reapir...
510
0.118
UMC 28nm HPC process Dual Port SRAM with row repair & LVT
UMC 28nm HPC process Dual Port SRAM with row repair & LVT...
511
0.118
UMC 28nm HPC process One Port Register File with LVT
UMC 28nm HPC process One Port Register File with LVT...
512
0.118
UMC 28nm HPC process PG Dual Port SRAM with LVT
UMC 28nm HPC process PG Dual Port SRAM with LVT...
513
0.118
UMC 28nm HPC process PG Two Port Register File
UMC 28nm HPC process PG Two Port Register File...
514
0.118
UMC 28nm HPC process PG Two Port Register File with peri-HVT
UMC 28nm HPC process PG Two Port Register File with peri-HVT...
515
0.118
UMC 28nm HPC process PG Two Port Register File with peri-LVT
UMC 28nm HPC process PG Two Port Register File with peri-LVT...
516
0.118
UMC 28nm HPC Process PG Via ROM Compiler
UMC 28nm HPC Process PG Via ROM Compiler...
517
0.118
UMC 28nm HPC process PG-2PRF with Bank4
UMC 28nm HPC process PG-2PRF with Bank4...
518
0.118
UMC 28nm HPC process PG-2PRF with HVT Bank4
UMC 28nm HPC process PG-2PRF with HVT Bank4...
519
0.118
UMC 28nm HPC process PG-2PRF with LVT and Bank 2
UMC 28nm HPC process PG-2PRF with LVT and Bank 2...
520
0.118
UMC 28nm HPC process PG-Dual Port SRAM with LVT
UMC 28nm HPC process PG-Dual Port SRAM with LVT...
521
0.118
UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler.
UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler....
522
0.118
UMC 28nm HPC process standard synchronous high density single port low power SRAM memory compiler with row redundancy
UMC 28nm HPC process standard synchronous high density single port low power SRAM memory compiler with row redundancy...
523
0.118
UMC 28nm HPC process standard synchronous HVT periphery high density single port low power SRAM memory compiler with row redundancy
UMC 28nm HPC process standard synchronous HVT periphery high density single port low power SRAM memory compiler with row redundancy...
524
0.118
UMC 28nm HPC process standard synchronous LVT periphery high density single port low power SRAM memory compiler with row redundancy
UMC 28nm HPC process standard synchronous LVT periphery high density single port low power SRAM memory compiler with row redundancy...
525
0.118
UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler....
526
0.118
UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler.
UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler....
527
0.118
UMC 28nm HPC process Two Port Register File
UMC 28nm HPC process Two Port Register File...
528
0.118
UMC 28nm HPC process Two Port Register File with Bank2
UMC 28nm HPC process Two Port Register File with Bank2...
529
0.118
UMC 28nm HPC process Two Port Register File with LVT and Bank2
UMC 28nm HPC process Two Port Register File with LVT and Bank2...
530
0.118
UMC 28nm HPC process Two Port Register File with LVT and Bank4
UMC 28nm HPC process Two Port Register File with LVT and Bank4...
531
0.118
UMC 28nm HPC process Two Port Register File with peri LVT
UMC 28nm HPC process Two Port Register File with peri LVT...
532
0.118
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler...
533
0.118
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT...
534
0.118
UMC 28nm HPC Process Ultra High Speed Single-Port SRAM memory compiler
UMC 28nm HPC Process Ultra High Speed Single-Port SRAM memory compiler...
535
0.118
UMC 28nm HPC Process Ultra High Speed Single-Port SRAM Memory Compiler
UMC 28nm HPC Process Ultra High Speed Single-Port SRAM Memory Compiler...
536
0.118
UMC 28nm HPM process standard synchronous high density single port SRAM memory compiler
UMC 28nm HPM process standard synchronous high density single port SRAM memory compiler...
537
0.118
UMC 28nm HPM process synchronous LVT preiphery high density single port SRAM memory compiler with Row and 2 Column Repair
UMC 28nm HPM process synchronous LVT preiphery high density single port SRAM memory compiler with Row and 2 Column Repair...
538
0.118
UMC 28nm HPM ultra high speed register compiler
UMC 28nm HPM ultra high speed register compiler...
539
0.118
UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler.
UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler....
540
0.118
UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler.
UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler....
541
0.118
UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy.
UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy....
542
0.118
UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler.
UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler....
543
0.118
UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler.
UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler....
544
0.118
UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler.
UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler....
545
0.118
UMC 40nm Low Power Process , Two Port Register File with dual power rail
UMC 40nm Low Power Process , Two Port Register File with dual power rail...
546
0.118
UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail
UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail...
547
0.118
UMC 40nm Low Power Process One Port Register File wit 213 cell
UMC 40nm Low Power Process One Port Register File wit 213 cell...
548
0.118
UMC 40nm Low Power Process One Port Register File with 213 cell
UMC 40nm Low Power Process One Port Register File with 213 cell...
549
0.118
UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell
UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell...
550
0.118
UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating
UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating...
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